The present invention relates to integrated circuits, and in particular, to an integrated circuit using a silicon substrate with isolation trenches formed therein for isolating the different elements of the integrated circuit.
Referring initially to FIG. 1, a substrate 1 made of a semiconductor material includes two adjacent isolation trenches 21. The isolation trenches 21 are usually formed in the substrate 1 at the beginning of the manufacturing process, and are separated by active areas 5 that contain the different elements of the integrated circuit, such as transistors, diodes, resistances and capacitors, for example. Each isolation trench 21 includes sides 2 and a bottom 3, and is full of an electrically insulating material 20. In circuits made of silicon, which is by far the most frequently used semiconductor material in the microelectronics industry, the electrically insulating material 20 is silicon oxide.
Attempts have been made to reduce the surface dimensions of the trenches 21 to reduce the area of the integrated circuit. It is also desirable that the dielectric constant of the material filling the trench 21 be as low as possible to reduce the coupling capacitance between two elements of the integrated circuit located on opposite sides of the trench.
Since circuits are becoming more and more miniaturized, two adjacent isolation trenches 21 are very close to each other. The presence of a large amount of the electrically insulating material in the semiconductor substrate 1 generates mechanically stressed areas in the semiconductor material. This is because the electrically insulating material and the semiconductor material have very different coefficients of thermal expansion. The mechanically stressed areas start from the sides 2 and the bottom 3 of a trench 21, and extend towards the adjacent trench. These mechanical stresses are greater when the sides 2 of the trenches 21 are not tapered outwards from the bottom 3.
In FIG. 1, stress lines 4 are shown in the substrate 1 around the illustrated trenches 21. The areas in which the trenches 21 are closest together are the areas in which the highest stresses occur. If the intensity of the stresses is to high, the yield stress of the semiconductor material will be exceeded. This causes dislocations in the semiconductor material, which makes the integrated circuit unusable.
In view of the foregoing background, an object of the present invention is to provide an isolation trench structure which has a low coupling capacitance but does not induce high mechanical stresses in the substrate, even if the trench is very close to other trenches of the same type.
This and other objects, advantages and features in accordance with the present invention are provided by an isolation trench having a bottom and sides in a semiconductor substrate, and spacers facing each other are added onto the sides. These spacers are designed to form a narrow channel between the sides of the trench in the substrate. The bottom and the spacers are preferably coated with an electrically insulating material for delimiting a closed empty cavity.
The spacers may also be made from an electrically insulating material. Closing the cavity is done using a plug made by the electrically insulating material that coats the sides and the bottom. The plug is positioned below an upper surface of the substrate. By introducing this empty cavity, the quantity of electrically insulating material used is lower than that used in isolation trenches full of the electrically insulating material.
The empty cavity does not contain any solid material, and is full of air and/or residual gases. This reduces the isolation capacity of the trench, since the relative permittivity of the air or gases is on the order of 1. The relative permittivity of the electrically insulating coating material and the electrically insulating material from which the spacers are made is greater than 1, since silicon oxide with a relative permittivity of more than 4 is usually used.
The sides of each trench may be approximately parallel over the entire depth of the trench, but the sides are preferably tapered outwards from the bottom. This shape more efficiently prevents the appearance of dislocations in the substrate material. The sides may be approximately parallel at the end opposite the bottom, which is close to the opening. The bottom is usually flat.
The shape factor of the narrow channel is preferably greater than 1. This parameter is important in forming and closing the empty cavity. The spacers may be parallel or even tapered inwards from the bottom, and then taper outwards or become parallel to the surface of the substrate. The spacers may also be set back from the surface of the substrate to control the depth of the closing plug.
The present invention is also directed to an integrated circuit provided with at least one isolation trench as defined above. The integrated circuit may also comprise at least one second isolation trench that is wider than the isolation trench as also defined above. The second isolation trench includes a bottom and sides, with the sides having spacers thereon and facing each other for defining a narrow channel therebetween. The channel is full of electrically insulating material. The wider isolation trench is preferably made at the same time as the first isolation trench which has the empty cavity included therein.
Another aspect of the present invention is directed to a process for forming an isolation trench in a semiconductor substrate. The process preferably comprises etching the substrate to form sides and a bottom of the isolation trench, and depositing an electrically insulating material on the bottom and sides to form spacers facing each other.
The method further comprises etching the spacers to delimit a narrow channel between the sides in the substrate, and depositing an electrically insulating material that coats the spacers and the bottom for delimiting a closed empty cavity.
The process may comprise a thermal annealing before depositing the electrically insulating material to make the spacers, and to restore the surface condition of the sides and the bottom. The electrically insulating material that coats the spacers and the bottom may be doped, and the thermal annealing may be carried out after it is deposited so that the insulating material creeps.
When the empty cavity is closed using a closing plug that is recessed from the surface, the process may include a new step of depositing an electrically insulating material to fill in the recess. A polishing step may also be added to eliminate surplus electrically insulating material on the surface of the semiconductor substrate.
Depositing the electrically insulating material for coating the spacers and the bottom of the isolation trench also coats the spacers and a bottom of a wider isolation trench that may be formed in the semiconductor substrate without delimiting the closed empty cavity in the isolation trench. The process may further comprise depositing an electrically insulating material to completely fill the wider isolation trench.